Ultralow contact resistance between metal and semiconductor

Why it matters

Stuffing more transistors into a limited amount of footprint has always been a goal in semiconductor industry. It is well-known that Moore's Law has come to an end due to the limitation imposed by the lattice structure of Si, whose ultra-thin form is hard to tailor due to the quantum effects and the surface dangling bonds. When the channel length shrinks (which essentially determines the footprint of a single transistor), the thickness of channel materials needs to shrink too because the aspect ratio of the channel material determines how good the back gate can control the whole channel. Simply imagine that you are cooking a pancake: if the batter is too thick on the pan, you probably get it burnt on the bottom while the top is still uncooked. This, as well, applies to transistors: if the channel is too thick, the effect of back gate (used for controlling the on/off state of the channel) cannot reach all the way to the top of the material due to the effect coming from the contacting electrodes on both sides. If you are interested, please check "short channel effects" on Google and you will see lots of problems created by shrinking the channel size. So in short, for channel materials, the thinner the better.

Currently, there are two major strategies to shrink the transistor. The first strategy is to redesign the structure of transistor on a Si-based technology, so the sophisticated synthesis techniques can be readily transferred. The current mainstream FinFET technology is one of such examples, where the gate wraps up three sides of the channel material to retain a better controllability of electronic states of Si (now you are essentially cooking the pancake with three sides, so it can be heat up more uniformly). This is a compromise to the limitation of the thickness that Si can achieve. As you can imagine, to extend this idea further, you need to completely wrap up the channel materials with four sides, which is exactly what the industry is doing. Another strategy is to completely switch the material from Si to other materials that has better semiconductor properties when it is made to be ultra-thin. Two-dimensional (2D) material, like MoS2, falls into this category, as it is intrinsically a monolayer material when exfoliated to its minimum thickness and it is free of dangling bonds in such 2D state. Theoretically, with a monolayer 2D semiconductor, we can overcome a lot of short channel effects associated with 3D semiconductors and reach sub-1-nm node technology, in principle. In reality, however, this ideal scenario is still hard to reach. One of the biggest problems with 2D semiconductor is the contact resistance between metal electrode and the monolayer semiconductor material (molybdenum disulfide, MoS2, in our case). A great amount of resistance comes from the so-called Schottky Barrier when metal and semiconductor is in contact with each other. This barrier is totally unwanted and can be attributed to a lot of performance degradation and heat problems in the device. It has been a problem on monolayer semiconductors for many years but due to an effect call Fermi level pinning, there was no way to get rid of it.

In our paper, we discovered that the contact between bismuth (Bi), a semimetal, and monolayer MoS2 has an ultra-low resistance close to the quantum limit, on par with the performance of the traditional semiconductors like Si, GaN, and InGaAs. Technically, we take advantage of the bond saturation of Bi surface and the zero density of state of Bi as a semimetal, and reach what we call "Gap State Saturation". The Schottky Barrier no longer exists between Bi and MoS2, so the whole monolayer device can reach a much better performance, which even surpasses Si if benchmarked by ON current per cross sectional area.

Note: Many news coverages and videos claim this work to be "a breakthrough of 1-nm node technology". While we agree it solves one of the biggest problems for creating monolayer transistors (which is indeed promising to be applied in 1-nm node technology), we didn't make an ultra-short channel device which meets the standard of 1-nm node in this work.

Figure: A schematic diagram shows the contact resistance in a transistor. Upper: when the device has big overall resistance, the current that goes through the device gets lower. Lower: Ideally, when the contact resistance is smaller, the performance of the device gets better.

Related Publications

  1. P.-C. Shen*, C. Su*(equal contribution), Y. Lin*, A.-S. Chou*, C.-C. Cheng, J.-H. Park, M.-H. Chiu, A.-Y.Lu, H.-L. Tang, M. Tavakoli, G. Pitner, X. Ji, Z. Cai, N. Mao, J. Wang, V. Tung, J. Li, J. Bokor, A. Zettl, C.-I. Wu, T. Palacios, L.-J. Li, and J. Kong, “Ultralow contact resistance between semimetal and monolayer semiconductors”, Nature, 593, 211–217 (2021).